AMS Design Verification Intern - Build Synthesizable Analog Models for Formal Verification (m/f/d)

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Connecticum Job-Nr. 1444658 / 200299064
  • Arbeitgeber: Apple
    Beschäftigungsart: Praktikum
    Jobdatum: 12. Oktober 2021
    Fachbereiche: Wirtschaftswissenschaften: Wirtschaftsinformatik, Wirtschaftsingenieurwesen
    Ingenieurwissenschaften: Elektrotechnik, Wirtschaftsingenieurwesen
    Informatik: Informatik, Technische Informatik, Wirtschaftsinformatik
    Einsatzort: München; Bayern
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    AMS Design Verification Intern - Build Synthesizable Analog Models for Formal Verification (m/f/d) - Jobangebot

    AMS Design Verification Intern - Build Synthesizable Analog Models for Formal Verification (m/f/d)
    Munich Bavaria-Bayern Germany
    Hardware
    Summary
    Posted: 12. Oct 2021
    Role Number: 200299064
    Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!

    The AMS IP team is responsible for a wide portfolio of IPs & complete subsystems going to all the Apple products. In this context the Design Verification Engineer collaborates with many different teams at Apple and builds knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to- end: starting at the specification level, defining verification strategy & plan, carrying out the verification, doing performance analysis, and handling all the different quality metrics to signoff the verification.
    Key Qualifications
    • Knowledge of Object Oriented Programming
      Knowledge of Verilog and/or VHDL
      Knowledge of Property Specification Language (SVA, ITL, …) or Formal Verification Techniques is a plus
      Scripting language knowledge (Perl/Python)
      Good written and verbal communication skills
      Excellent interpersonal skills and well-organised working style
      Ability to work well in an international team and be productive under tight schedules
      Availability for at least 6 months
    Description
    This internship requires strong background in OOP and solid knowledge about advanced software programming techniques. Knowledge about formal verification languages, techniques and tools will be acquired during the project. With mentorship, you will have to learn and develop the modelling approach for analog design that is suitable for formal verification as well as enabling the models for synthesis. You have the opportunity to learn state of art verification methodology, involve in define the analog model strategy. Your tasks include the following:

    - Learn different modelling approaches and aspects for the analog models
    - Apply formal verification to real life designs
    - Opportunity to enhance analog model strategy
    Education & Experience
    Currently enrolled in your penultimate year of studies in a CE, EE, CS or related field (Bachelor's, Master's or PhD).
    Additional Requirements
    • Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.
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AMS Design Verification Intern - Build Synthesizable Analog Models for Formal Verification (m/f/d)
Jobkennzeichen Connecticum Job-Nr. 1444658 / 200299064
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