Stellenbeschreibung - AMS Design Verification Engineer (m/f/d)
connecticum Job 1741987 / 200228405
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Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
Hands-on experience with constrained random verification environments Hands-on experience with Assertion Based Verification Basic design background in support of verification results analysis Knowledge of Object Oriented Programming (OOP) Familiarity with system design using C (C++) or Verilog is a plus ATE functional test pattern generation for logic testers is a plus Proficiency in English language is required
Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.
MSc in Electrical Engineering or industrial experience equivalent.
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Informationen zur Bewerbung
Stellenangebot:
AMS Design Verification Engineer (m/f/d)
Jobkennzeichen:
Connecticum Job 1741987 / 200228405
Bereiche:
Wirtschaftswissenschaften:
Wirtschaftsinformatik, Wirtschaftsingenieurwesen
Ingenieurwissenschaften:
Allg. Ingenieurwissenschaften, Elektrotechnik, Wirtschaftsingenieurwesen
Informatik:
Informatik, Technische Informatik, Wirtschaftsinformatik