CAD Extraction Engineer (M, F, D)

- Stellenanzeige | Apple

Arbeitgeber: Apple

Jobdatum: 25. April 2024

Einsatzort: München; Bayern

Stellenbeschreibung - CAD Extraction Engineer (M, F, D)

connecticum Job 1745141 / 200506318

CAD Extraction Engineer (M, F, D)

Posted: 13. Feb 2024

Role Number: 200506318

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance of every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do everything they love with their devices! In the CAD organization, you will create new software and technologies enabling other Apple engineers to develop products for millions of customers worldwide!

Key Qualifications

Are familiar with post-layout custom design flow, including LVS, Extraction, and Simulations.

Bring experience as a power user or developer with extraction tools like StarRC and Quantus.

Have a deep understanding of cellular/wireless design RC accuracy investigation, reduction methods, and simulation impact.

Have skills in sophisticated script development using Shell, Perl, Python, and TCL.

Understand foundry PDK collaterals and usage in individual flows.

Bring a general problem-solving attitude and positive teamwork.

Experience in general big data analysis is a plus.

Ability to fluently speak and write in English.

Description

As a member of our CAD team, you will develop, maintain, and enhance existing parasitics extraction flow for Apple’s successful silicon designs.
You will use the most efficient RC analysis skills on various designs to diagnose and debug parasitic effects and guide and design improvement for balanced and minimized parasitic impact.
Your experience and proficient usage of EDA extraction tools and methodologies will ensure parasitic RLC accuracy and circuit performance in post-layout simulations.
You must deeply understand parasitic modeling in advanced process technologies and use the knowledge to explain circuit behavior and performance.
You will work closely with EDA vendors to incorporate new capabilities to solve technical problems.
You can develop an RC-aware or RC-driven methodology for design optimization.

Education & Experience

BS/MS degree in a relevant technical field like Electrical Engineering.

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