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Design Verification Engineer

Stellenangebot von Apple

: Job-Details
: Einsatzort

Connecticum Job-Nr. 1228299 / 200013298

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Beschäftigungsarten:	Praktikum Junior Professional Senior Professional
Arbeitgeber:	Apple
Jobdatum:	24. Dezember 2020
Studienbereiche:	Wirtschaftswissenschaften: Wirtschaftsinformatik, Wirtschaftsingenieurwesen Ingenieurwissenschaften: Allg. Ingenieurwissenschaften, Elektrotechnik, Wirtschaftsingenieurwesen Informatik: Informatik, Technische Informatik, Wirtschaftsinformatik
Einsatzorte:	München; Bayern

Stellenangebot: Design Verification Engineer

Design Verification Engineer

Posted: 27. Jan 2021

Role Number: 200013298

At Apple, we work every day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our multifaceted group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.

Do your life’s best work here at Apple! This role is for a Design Verification engineer who will enable bug-free first silicon for the mixed-signal designs in our Munich office. The responsibilities include all phases of pre-silicon verification including but not limited to: construction of verification environments, coding of test scenarios and assertions and close collaboration with Analog and Digital Design engineers.

Key Qualifications

Deep knowledge of System Verilog test-bench language and UVM
Hands-on experience with constrained random verification environments
Hands-on experience with Assertion Based Verification
Basic design background in support of verification results analysis
Knowledge of Object Oriented Programming
Familiarity with system design using C (C++) or Verilog is a plus
ATE functional test pattern generation for logic testers is a plus
Recent MSc graduates with outstanding academic results and relevant internship experiences will also be considered

Description

Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.

Education & Experience

MSc in Electrical Engineering or industrial experience equivalent.

Additional Requirements

Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.